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IPPS
2005
IEEE
15 years 3 months ago
Configuration Steering for a Reconfigurable Superscalar Processor
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
Brian F. Veale, John K. Antonio, Monte P. Tull
58
Voted
FPL
2008
Springer
103views Hardware» more  FPL 2008»
14 years 11 months ago
No-break dynamic defragmentation of reconfigurable devices
We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules ...
Sándor P. Fekete, Tom Kamphans, Nils Schwee...
71
Voted
ERSA
2006
100views Hardware» more  ERSA 2006»
14 years 11 months ago
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
Markus Koester, Heiko Kalte, Mario Porrmann
75
Voted
IPPS
1998
IEEE
15 years 1 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl...
CONCUR
2008
Springer
14 years 11 months ago
Dynamic Partial Order Reduction Using Probe Sets
We present an algorithm for partial order reduction in the context of a countable universe of deterministic actions, of which finitely many are enabled at any given state. This mea...
Harmen Kastenberg, Arend Rensink