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FCCM
1998
IEEE
148views VLSI» more  FCCM 1998»
15 years 1 months ago
JHDL - An HDL for Reconfigurable Systems
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
Peter Bellows, Brad L. Hutchings
SIGPLAN
2008
14 years 9 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
MIDDLEWARE
2005
Springer
15 years 3 months ago
A reconfigurable group management middleware service for wireless sensor networks
Group management service plays a key role in wireless sensor networks (WSNs) as it provides support to high level middleware services such as object tracking, security, fault-tole...
Mardoqueu Vieira, Nelson Souto Rosa
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FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
15 years 4 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
IFIP
1998
Springer
15 years 1 months ago
Combining Static Partitioning with Dynamic Distribution of Threads
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
Ronald Moore, Melanie Klang, Bernd Klauer, Klaus W...