269 search results - page 42 / 54 » Parallel performance tuning for Haskell |
95
Voted
ICPP
2003
IEEE
15 years 5 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
107
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MSS
2003
IEEE
15 years 5 months ago
2003
IEEE
: Several solutions have been developed to provide dataintensive applications with the highest possible data rates. Such solutions tried to utilize the available network resources ...
102
Voted
ICPP
2002
IEEE
15 years 5 months ago
2002
IEEE
The development and implementation of new network protocols and applications need accurate, scalable, reconfigurable, and inexpensive tools for debugging, testing, performance tun...
118
Voted
IPPS
1998
IEEE
15 years 4 months ago
1998
IEEE
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
124
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EH
2004
IEEE
15 years 4 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...