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» Parallel placement for field-programmable gate arrays
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89
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DAC
2002
ACM
16 years 18 days ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
EUC
2005
Springer
15 years 5 months ago
Evaluation of Space Allocation Circuits
This paper describes the design and evaluation of the PCA (Plastic Cell Architecture) cell, which implements a novel space allocation method. PCA is a dynamically reconfigurable a...
Shinya Kyusaka, Hayato Higuchi, Taichi Nagamoto, Y...
ACSC
2004
IEEE
15 years 3 months ago
Exploiting FPGA Concurrency to Enhance JVM Performance
The Java Programming Language has been praised for its platform independence and portability, but because of its slow execution speed on a software Java Virtual Machine (JVM), som...
James Parnis, Gareth Lee
93
Voted
JRTIP
2008
118views more  JRTIP 2008»
14 years 11 months ago
Custom parallel caching schemes for hardware-accelerated image compression
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...
Su-Shin Ang, George A. Constantinides, Wayne Luk, ...
106
Voted
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 8 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras