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» Parallel placement for field-programmable gate arrays
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ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
15 years 4 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
85
Voted
FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
15 years 4 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
72
Voted
ISVC
2007
Springer
15 years 3 months ago
Motion Projection for Floating Object Detection
Abstract. Floating mines are a significant threat to the safety of ships in theatres of military or terrorist conflict. Automating mine detection is difficult, due to the unpredict...
Zhaoyi Wei, Dah-Jye Lee, David Jilk, Robert B. Sch...
92
Voted
ICPADS
2006
IEEE
15 years 3 months ago
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
Ling Zhuo, Viktor K. Prasanna
79
Voted
EVOW
2003
Springer
15 years 2 months ago
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages
Evolutionary Algorithms (EAs) have been proposed as a very powerful heuristic optimization technique to solve complex problems. Many case studies have shown that they work very eff...
Rolf Drechsler, Nicole Drechsler