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» Parallel placement for field-programmable gate arrays
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FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
15 years 2 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
70
Voted
FPL
1998
Springer
82views Hardware» more  FPL 1998»
15 years 1 months ago
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
Abstract. Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-le...
Wayne Luk, Steve McKeever
TCSV
2008
120views more  TCSV 2008»
14 years 9 months ago
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
Abstract--This paper proposes a parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm and applied to the SLAM (...
Vanderlei Bonato, Eduardo Marques, George A. Const...
68
Voted
ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
15 years 4 months ago
Algorithm for parallel inverse halftoning using partitioning of Look-Up Table (LUT)
— The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose a new algorithm to ...
Umair F. Siddiqi, Sadiq M. Sait
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
15 years 6 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras