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» Parallel processing flow models on desktop hardware
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CASES
2001
ACM
15 years 1 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...
ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
15 years 2 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
ICCS
2004
Springer
15 years 3 months ago
A Two-Leveled Mobile Agent System for E-commerce with Constraint-Based Filtering
This paper presents a two-leveled mobile agent system for electronic commerce. It is based on mobile agents as mediators and uses the publish/subscribe paradigm for registration an...
Ozgur Koray Sahingoz, Nadia Erdogan
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 2 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
IEEEPACT
2007
IEEE
15 years 4 months ago
Architectural Support for the Stream Execution Model on General-Purpose Processors
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mende...