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» Parallel processing flow models on desktop hardware
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SPAA
2006
ACM
15 years 4 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
PPOPP
2003
ACM
15 years 3 months ago
Automated application-level checkpointing of MPI programs
Because of increasing hardware and software complexity, the running time of many computational science applications is now more than the mean-time-to-failure of highpeformance com...
Greg Bronevetsky, Daniel Marques, Keshav Pingali, ...
EUROPAR
2003
Springer
15 years 3 months ago
A Coordination Model for ad hoc Mobile Systems
The growing success of wireless ad hoc networks and portable hardware devices presents many interesting problems to software engineers. Particular, coordination is a challenging t...
Marco Tulio de Oliveira Valente, Fernando Magno Qu...
PDCN
2004
14 years 11 months ago
Design and implementation of a network simulation system
In this paper, an efficient tool has been designed and implemented to design and analyze the communication networks. A network simulator in software is valuable for network manage...
Jae-Weon Choi, Man-Hui Lee
ITC
1998
IEEE
174views Hardware» more  ITC 1998»
15 years 2 months ago
High volume microprocessor test escapes, an analysis of defects our tests are missing
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...
Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong