360 search results - page 63 / 72 » Parallel processing flow models on desktop hardware |
91
Voted
DATE
2005
IEEE
15 years 6 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
108
Voted
3DIM
2007
IEEE
16 years 13 days ago
2007
IEEE
Object pose (location and orientation) estimation is a
common task in many computer vision applications. Although
many methods exist, most algorithms need manual
initialization ...
92
Voted
EUROPAR
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. To analyze the correctness and the performance of a program, information about the dynamic behavior of all participating processes is needed. The dynamic behavior can be ...
101
Voted
CF
2006
ACM
15 years 4 months ago
2006
ACM
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
116
click to vote
CASES
2006
ACM
15 years 4 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...