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» Parallel processing flow models on desktop hardware
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DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 22 days ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 8 days ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
CORR
2011
Springer
197views Education» more  CORR 2011»
13 years 1 months ago
High-Throughput Transaction Executions on Graphics Processors
OLTP (On-Line Transaction Processing) is an important business system sector in various traditional and emerging online services. Due to the increasing number of users, OLTP syste...
Bingsheng He, Jeffrey Xu Yu
HPCA
2003
IEEE
14 years 6 months ago
Memory System Behavior of Java-Based Middleware
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...
Martin Karlsson, Kevin E. Moore, Erik Hagersten, D...
ICPP
2002
IEEE
13 years 11 months ago
Software Caching using Dynamic Binary Rewriting for Embedded Devices
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...
Chad Huneycutt, Joshua B. Fryman, Kenneth M. Macke...