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DSN
2007
IEEE
15 years 6 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
IEEEPACT
2005
IEEE
15 years 5 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher
CLUSTER
2003
IEEE
15 years 5 months ago
Implications of a PIM Architectural Model for MPI
Memory may be the only system component that is more commoditized than a microprocessor. To simultaneously exploit this and address the impending memory wall, processing in memory...
Arun Rodrigues, Richard C. Murphy, Peter M. Kogge,...
IV
1999
IEEE
91views Visualization» more  IV 1999»
15 years 4 months ago
Triangle Mesh Compression for Fast Rendering
Modern GIS(Geographic Information System) application programs and simulation systems have to handle large datasets for rendering. Currently three dimensional rendering hardware a...
Dong-Gyu Park, Yang-Soo Kim, Hwan-Gue Cho
CASES
2001
ACM
15 years 3 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu