13 search results - page 2 / 3 » Parallel simulated annealing strategies for VLSI cell placem... |
IPPS
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM...
CATA
2007
14 years 11 months ago
2007
In this paper, Simulated Evolution based goodness attributes are incorporated into Tabu Search and Genetic Algorithms to enhance performance as compared to canonical strategies. I...
ICCSA
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. In this paper, we present a parallel tabu search (TS) algorithm for efficient optimization of a constrained multiobjective VLSI standard cell placement problem. The prima...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...