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» Parallel simulation of chip-multiprocessor architectures
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IPPS
2010
IEEE
14 years 12 months ago
Improving the performance of Uintah: A large-scale adaptive meshing computational framework
Abstract--Uintah is a highly parallel and adaptive multiphysics framework created by the Center for Simulation of Accidental Fires and Explosions in Utah. Uintah, which is built up...
Justin Luitjens, Martin Berzins
DAC
2005
ACM
16 years 2 months ago
StressTest: an automatic approach to test generation via activity monitors
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
HPCA
2004
IEEE
16 years 2 months ago
Exploiting Prediction to Reduce Power on Buses
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
Victor Wen, Mark Whitney, Yatish Patel, John Kubia...
IEEEPACT
2003
IEEE
15 years 7 months ago
Redeeming IPC as a Performance Metric for Multithreaded Programs
Recent work has shown that multithreaded workloads running in execution-driven, full-system simulation environments cannot use instructions per cycle (IPC) as a valid performance ...
Kevin M. Lepak, Harold W. Cain, Mikko H. Lipasti
110
Voted
HPDC
2006
IEEE
15 years 8 months ago
Path Grammar Guided Trace Compression and Trace Approximation
Trace-driven simulation is an important technique used in the evaluation of computer architecture innovations. However using it for studying parallel computers and applications is...
Xiaofeng Gao, Allan Snavely, Larry Carter