770 search results - page 119 / 154 » Parallel simulation of chip-multiprocessor architectures |
ASYNC
2003
IEEE
15 years 5 months ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
DEBS
2003
ACM
15 years 5 months ago
2003
ACM
Overlay broker networks are an important part of an eventbased middleware. In this paper, we investigate the requirements of overlay broker networks and argue that using peer-to-p...
EH
1999
IEEE
15 years 4 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
104
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ISCA
1993
IEEE
15 years 3 months ago
1993
IEEE
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
106
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BIBE
2007
IEEE
15 years 1 months ago
2007
IEEE
In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...