770 search results - page 131 / 154 » Parallel simulation of chip-multiprocessor architectures |
147
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VLSISP
2008
15 years 5 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
141
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HPCA
2003
IEEE
16 years 5 months ago
2003
IEEE
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...
145
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ISLPED
2004
ACM
15 years 10 months ago
2004
ACM
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
128
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HPCA
2007
IEEE
16 years 5 months ago
2007
IEEE
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...
154
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ASIAMS
2007
IEEE
15 years 11 months ago
2007
IEEE
The tree structure has received much interest as a versatile architecture for a large class of parallel processing applications. Spanning trees in particular are essential tools f...