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» Parallel simulation of chip-multiprocessor architectures
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HPCA
2009
IEEE
16 years 8 days ago
A first-order fine-grained multithreaded throughput model
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...
Xi E. Chen, Tor M. Aamodt
PPOPP
2010
ACM
15 years 9 months ago
Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
Eddy Z. Zhang, Xipeng Shen, Yunlian Jiang
234
Voted
ASPLOS
2009
ACM
16 years 11 days ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
94
Voted
IEEEPACT
2009
IEEE
15 years 6 months ago
Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
Leo Porter, Bumyong Choi, Dean M. Tullsen
PDP
2010
IEEE
15 years 4 months ago
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
Antonio Flores, Juan L. Aragón, Manuel E. A...