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» Parallel simulation of chip-multiprocessor architectures
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TPDS
2002
117views more  TPDS 2002»
15 years 1 months ago
Gemini: An Optical Interconnection Network for Parallel Processing
Abstract--The Gemini interconnect is a dual technology (optical and electrical) interconnection network designed for use in tightlycoupled multicomputer systems. It consists of a c...
Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi ...
IEEEPACT
2000
IEEE
15 years 6 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
ICCS
2003
Springer
15 years 7 months ago
Performance Analysis of a Parallel Application in the GRID
Performance analysis of real applications in clusters and GRID like environments is essential to fully exploit the performance of new architectures. The key problem is the deepenin...
Holger Brunst, Edgar Gabriel, Marc Lange, Matthias...
HPCA
2003
IEEE
16 years 2 months ago
A Statistically Rigorous Approach for Improving Simulation Methodology
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
APCSAC
2001
IEEE
15 years 5 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li