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» Parallel simulation of chip-multiprocessor architectures
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ICRA
2000
IEEE
141views Robotics» more  ICRA 2000»
15 years 6 months ago
Haptic Rendering of Planar Rigid-Body Motion using a Redundant Parallel Mechanism
We present a system for rendering planar rigid-body motion by means of a redundant parallel mechanism. The device design, the control architecture and the passive virtual environm...
Daniela Constantinescu, Icarus Chau, Simon P. DiMa...
SIGGRAPH
2000
ACM
15 years 6 months ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
CLUSTER
2009
IEEE
14 years 11 months ago
MITHRA: Multiple data independent tasks on a heterogeneous resource architecture
With the advent of high-performance COTS clusters, there is a need for a simple, scalable and faulttolerant parallel programming and execution paradigm. In this paper, we show that...
Reza Farivar, Abhishek Verma, Ellick Chan, Roy H. ...
ISCAS
2007
IEEE
105views Hardware» more  ISCAS 2007»
15 years 8 months ago
Parallel current-steering D/A Converters for Flexibility and Smartness
—This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of avai...
Georgi I. Radulov, Patrick J. Quinn, Pieter Harpe,...
SIGMETRICS
1995
ACM
144views Hardware» more  SIGMETRICS 1995»
15 years 5 months ago
On Characterizing Bandwidth Requirements of Parallel Applications
Synthesizing architectural requirements from an application viewpoint can help in making important architectural design decisions towards building large scale parallel machines. I...
Anand Sivasubramaniam, Aman Singla, Umakishore Ram...