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» Parallel simulation of chip-multiprocessor architectures
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IPPS
2009
IEEE
15 years 8 months ago
Early experiences on accelerating Dijkstra's algorithm using transactional memory
In this paper we use Dijkstra’s algorithm as a challenging, hard to parallelize paradigm to test the efficacy of several parallelization techniques in a multicore architecture....
Nikos Anastopoulos, Konstantinos Nikas, Georgios I...
ICPADS
2008
IEEE
15 years 8 months ago
Quarc: A Novel Network-On-Chip Architecture
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC [16]. The Quarc scheme significantly outperforms the Spidergon NoC through balancing t...
Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi
IPPS
2006
IEEE
15 years 8 months ago
FPGA based architecture for DNA sequence comparison and database search
DNA sequence comparison is a computationally intensive problem, known widely since the competition for human DNA decryption. Database search for DNA sequence comparison is of grea...
Euripides Sotiriades, Christos Kozanitis, Apostolo...
HPCA
1998
IEEE
15 years 5 months ago
Non-Stalling CounterFlow Architecture
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu
ICPP
2009
IEEE
15 years 8 months ago
Complexity Analysis and Performance Evaluation of Matrix Product on Multicore Architectures
The multicore revolution is underway, bringing new chips introducing more complex memory architectures. Classical algorithms must be revisited in order to take the hierarchical me...
Mathias Jacquelin, Loris Marchal, Yves Robert