770 search results - page 60 / 154 » Parallel simulation of chip-multiprocessor architectures |
ISCA
1997
IEEE
15 years 6 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
125
click to vote
PLDI
1995
ACM
15 years 5 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
153
click to vote
IJVR
2006
15 years 1 months ago
2006
Real time terrain rendering plays a very important role in many fields, such of GIS, virtual reality, and military simulations. With the rapid development of PC-level hardware, rec...
112
click to vote
ISCC
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract—This paper presents a novel scalable switching architecture for input queued switches with its proper arbitration algorithms. In contrast to traditional switching archit...
114
click to vote
ISLPED
1996
ACM
15 years 6 months ago
1996
ACM
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...