770 search results - page 62 / 154 » Parallel simulation of chip-multiprocessor architectures |
127
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DAC
2006
ACM
16 years 2 months ago
2006
ACM
This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...
134
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DAC
2010
ACM
15 years 2 months ago
2010
ACM
Decoupling capacitor (decap) placement has been widely adopted as an effective way to suppress dynamic power supply noise. Traditional decap budgeting algorithms usually explore t...
DAC
2008
ACM
2008
ACM
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
16 years 3 months ago
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
113
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CCGRID
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper describes the integration of the High Level Architecture (HLA), an IEEE standard for distributed interactive simulation, with a scientific software package (Scilab) and...
117
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IPPS
1999
IEEE
15 years 6 months ago
1999
IEEE
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...