770 search results - page 90 / 154 » Parallel simulation of chip-multiprocessor architectures |
153
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HOTI
2011
IEEE
14 years 1 months ago
2011
IEEE
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
147
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SIPS
2008
IEEE
15 years 8 months ago
2008
IEEE
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
113
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IPPS
2006
IEEE
15 years 8 months ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
120
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IPPS
2003
IEEE
15 years 7 months ago
2003
IEEE
In this paper we propose a novel architecture, CARD, for resource discovery in large scale MANets that may scale up to thousands of nodes. Our mechanism is suitable for resource d...
112
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ISCA
2006
IEEE
15 years 8 months ago
2006
IEEE
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...