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» Parallel simulation of chip-multiprocessor architectures
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MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
15 years 8 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...
ICS
2009
Tsinghua U.
15 years 8 months ago
Dynamic topology aware load balancing algorithms for molecular dynamics applications
Molecular Dynamics applications enhance our understanding of biological phenomena through bio-molecular simulations. Large-scale parallelization of MD simulations is challenging b...
Abhinav Bhatele, Laxmikant V. Kalé, Sameer ...
ASPLOS
2000
ACM
15 years 6 months ago
An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture
This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years,...
Joshua Redstone, Susan J. Eggers, Henry M. Levy
ICS
1999
Tsinghua U.
15 years 6 months ago
Low-level router design and its impact on supercomputer system performance
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
Valentin Puente, José A. Gregorio, Cruz Izu...
ISCAS
2007
IEEE
169views Hardware» more  ISCAS 2007»
15 years 8 months ago
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequ...
Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang