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» Parallel simulation of chip-multiprocessor architectures
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HOTI
2005
IEEE
15 years 7 months ago
A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network
We present SPINet (Scalable Photonic Integrated Network), an optical switching architecture particularly designed for photonic integration. The performance of SPINet-based network...
Assaf Shacham, Benjamin G. Lee, Keren Bergman
CORR
2010
Springer
198views Education» more  CORR 2010»
15 years 2 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka
ICDCS
2000
IEEE
15 years 6 months ago
Dynamic Adaptive File Management in a Local Area Network
In light of advances in processor and networking technology, especially the emergenceof networkattached disks,the traditional clientserver architecture of file systems has become...
Jiong Yang, Wei Wang 0010, Richard R. Muntz, Silvi...
DSN
2003
IEEE
15 years 7 months ago
An Algorithm for Automatically Obtaining Distributed and Fault-Tolerant Static Schedules
Our goal is to automatically obtain a distributed and fault-tolerant embedded system: distributed because the system must run on a distributed architecture; fault-tolerant because...
Alain Girault, Hamoudi Kalla, Mihaela Sighireanu, ...
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ISPAN
2005
IEEE
15 years 7 months ago
A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars
Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling syst...
Kevin F. Chen, Edwin Hsing-Mean Sha, S. Q. Zheng