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» Parallel simulation of chip-multiprocessor architectures
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DAC
1994
ACM
15 years 6 months ago
Acyclic Multi-Way Partitioning of Boolean Networks
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
Jason Cong, Zheng Li, Rajive Bagrodia
143
Voted
CLUSTER
2004
IEEE
15 years 1 months ago
Performance Evaluation of Deflection Routing in Optical IP Packet-Switched Networks
In previous papers [5,6], an optical switch architecture was proposed to handle variable-length packets such as IP datagrams, based on an AWG device to route packets and equipped w...
Stefano Bregni, Achille Pattavina
COLCOM
2008
IEEE
15 years 8 months ago
Serial vs. Concurrent Scheduling of Transmission and Processing Tasks in Collaborative Systems
In collaboration architectures, a computer must perform both processing and transmission tasks. Intuitively, it seems that these independent tasks should be executed in concurrent ...
Sasa Junuzovic, Prasun Dewan
IASTEDSEA
2004
15 years 3 months ago
Instance orientation: A programming methodology
Instance orientation is an approach for designing and programming software systems. It addresses a limitation of current software architectures: it allows multiple higherlevel vie...
Thomas Schöbel-Theuer
ISCAS
2003
IEEE
105views Hardware» more  ISCAS 2003»
15 years 7 months ago
Algorithmic partial analog-to-digital conversion in mixed-signal array processors
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processor...
Roman Genov, Gert Cauwenberghs