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INFOCOM
1999
IEEE
15 years 8 months ago
High Performance IP Routing Table Lookup using CPU Caching
Wire-speed IP (Internet Protocol) routers require very fast routing table lookup for incoming IP packets. The routing table lookup operation is time consuming because the part of ...
Tzi-cker Chiueh, Prashant Pradhan
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 8 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
VISUALIZATION
1998
IEEE
15 years 8 months ago
Hierarchical volume analysis and visualization based on morphological operators
One common problem in the practical application of volume visualization is the proper choice of transfer functions in order to color different parts of the volume meaningfully. Th...
Christoph Lürig, Thomas Ertl
ASPLOS
1992
ACM
15 years 8 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
SIGGRAPH
1994
ACM
15 years 8 months ago
FBRAM: a new form of memory optimized for 3D graphics
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
Michael F. Deering, Stephen A. Schlapp, Michael G....
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