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150
Voted
ICPP
2008
IEEE
15 years 10 months ago
2008
IEEE
On systems with multi-core processors, the memory access scheduling scheme plays an important role not only in utilizing the limited memory bandwidth but also in balancing the pro...
134
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ICPP
2008
IEEE
15 years 10 months ago
2008
IEEE
—We address the recently recognized privatization problem in software transactional memory (STM) runtimes, and introduce the notion of partially visible reads (PVRs) to heuristic...
146
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IEEEPACT
2008
IEEE
15 years 10 months ago
2008
IEEE
The memory access limits the performance of stream processors. By exploiting the reuse of data held in the Stream Register File (SRF), an on-chip storage, the number of memory acc...
126
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IPPS
2008
IEEE
15 years 10 months ago
2008
IEEE
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
164
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SBACPAD
2008
IEEE
15 years 10 months ago
2008
IEEE
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...