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ICECCS
2010
IEEE
196views Hardware» more  ICECCS 2010»
15 years 3 months ago
Implementing and Evaluating a Model Checker for Transactional Memory Systems
Abstract—Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM ...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
IPPS
2010
IEEE
15 years 1 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
CLUSTER
2009
IEEE
15 years 1 months ago
Design alternatives for implementing fence synchronization in MPI-2 one-sided communication for InfiniBand clusters
Scientific computing has seen an immense growth in recent years. The Message Passing Interface (MPI) has become the de-facto standard for parallel programming model for distribute...
Gopalakrishnan Santhanaraman, Tejus Gangadharappa,...
107
Voted
DAC
2002
ACM
16 years 4 months ago
ILP-based engineering change
We have developed a generic integer linear programming(ILP)based engineering change(EC) methodology. The EC methodology has three components: enabling, fast, and preserving. Enabl...
Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng...
97
Voted
WWW
2008
ACM
16 years 4 months ago
Extending the compatibility notion for abstract WS-BPEL processes
WS-BPEL Processes Dieter K?nig IBM B?blingen Laboratory Sch?naicher Stra?e 220, 71032 B?blingen, Germany dieterkoenig@de.ibm.com Niels Lohmann Universit?t Rostock, Institut f?r Inf...
Dieter König, Niels Lohmann, Simon Moser, Chr...
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