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MASCOTS
2010
15 years 7 months ago
Efficient Discovery of Loop Nests in Execution Traces
Execution and communication traces are central to performance modeling and analysis. Since the traces can be very long, meaningful compression and extraction of representative beha...
Qiang Xu, Jaspal Subhlok, Nathaniel Hammen
MASCOTS
2007
15 years 7 months ago
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khon...
ERSA
2006
133views Hardware» more  ERSA 2006»
15 years 7 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
COLING
1996
15 years 7 months ago
Reversible delayed lexical choice in a bidirectional framework
We describe a bidirectional framework for natural language parsing and generation, using a typedfeatureformalismand an HPSG-based grammar with a parser and generator derived from ...
Graham Wilcock, Yuji Matsumoto
ISMB
1993
15 years 7 months ago
Protein Structure Prediction: Selecting Salient Features from Large Candidate Pools
Weintroduce a parallel approach, "DT-SELECT," for selecting features used by inductive learning algorithms to predict protein secondary structure. DT-SELECTis able to ra...
Kevin J. Cherkauer, Jude W. Shavlik
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