Sciweavers

6897 search results - page 676 / 1380
» Parallelization of Modular Algorithms
Sort
View
ICN
2005
Springer
16 years 15 days ago
Scheduling Algorithms for Input Queued Switches Using Local Search Technique
Input Queued switches have been very well studied in the recent past. The Maximum Weight Matching (MWM) algorithm is known to deliver 100% throughput under any admissible traffic. ...
Yanfeng Zheng, Simin He, Shutao Sun, Wen Gao
ICS
2004
Tsinghua U.
16 years 13 days ago
Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches
We propose a novel replacement algorithm, called InterReference Gap Distribution Replacement (IGDR), for setassociative secondary caches of processors. IGDR attaches a weight to e...
Masamichi Takagi, Kei Hiraki
PPSC
1989
15 years 8 months ago
Evaluating Block Algorithm Variants in LAPACK
The LAPACK software project currently under development is intended to provide a portable linear algebra library for high performance computers. LAPACK will make use of the Level 1...
Ed Anderson, Jack Dongarra
BMCBI
2010
132views more  BMCBI 2010»
15 years 7 months ago
Data structures and compression algorithms for high-throughput sequencing technologies
Background: High-throughput sequencing (HTS) technologies play important roles in the life sciences by allowing the rapid parallel sequencing of very large numbers of relatively s...
Kenny Daily, Paul Rigor, Scott Christley, Xiaohui ...
TVLSI
2010
15 years 1 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...