5802 search results - page 144 / 1161 » Parallelizing Feature Selection |
112
Voted
PAMI
2002
15 years 2 months ago
2002
109
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IEEEPACT
2009
IEEE
15 years 7 days ago
2009
IEEE
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
119
Voted
IPPS
2006
IEEE
15 years 8 months ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
123
Voted
EUROPAR
2011
Springer
14 years 2 months ago
2011
Springer
DOALL loops are tiled to exploit DOALL parallelism and data locality on GPUs. In contrast, due to loop-carried dependences, DOACROSS loops must be skewed first in order to make ti...
127
Voted
LCPC
2005
Springer
15 years 8 months ago
2005
Springer
Thread-level speculation (TLS) allows potentially dependent threads to speculatively execute in parallel, thus making it easier for the compiler to extract parallel threads. Howeve...