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» Parallelizing Feature Selection
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279
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ICS
2007
Tsinghua U.
16 years 26 days ago
Scheduling FFT computation on SMP and multicore systems
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
Ayaz Ali, S. Lennart Johnsson, Jaspal Subhlok
190
Voted
IPPS
2009
IEEE
16 years 1 months ago
Accelerating HMMer on FPGAs using systolic array based architecture
HMMer is a widely-used bioinformatics software package that uses profile HMMs (Hidden Markov Models) to model the primary structure consensus of a family of protein or nucleic aci...
Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan ...
ICPP
2005
IEEE
16 years 9 days ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...
GECCO
2008
Springer
137views Optimization» more  GECCO 2008»
15 years 7 months ago
Informative sampling for large unbalanced data sets
Selective sampling is a form of active learning which can reduce the cost of training by only drawing informative data points into the training set. This selected training set is ...
Zhenyu Lu, Anand I. Rughani, Bruce I. Tranmer, Jos...
170
Voted
ICS
2009
Tsinghua U.
16 years 1 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron