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» Parallelizing Functional Programs by Generalization
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ICS
2005
Tsinghua U.
15 years 3 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
BMCBI
2008
130views more  BMCBI 2008»
14 years 10 months ago
IDEA: Interactive Display for Evolutionary Analyses
Background: The availability of complete genomic sequences for hundreds of organisms promises to make obtaining genome-wide estimates of substitution rates, selective constraints ...
Amy Egan, Anup Mahurkar, Jonathan Crabtree, Jonath...
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
14 years 8 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 1 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
IEEEPACT
2008
IEEE
15 years 4 months ago
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
Katherine E. Coons, Behnam Robatmili, Matthew E. T...