47 search results - page 9 / 10 » Parallelizing HMMER for Hardware Acceleration on FPGAs |
PDCAT
2007
Springer
14 years 11 days ago
2007
Springer
ct There have been many previous attempts to accelerate MT19937 using FPGAs but we believe that we can substantially improve the previous implementations to develop a higher throug...
CF
2009
ACM
14 years 23 days ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
IPPS
1999
IEEE
13 years 10 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...