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ISPAN
2002
IEEE
15 years 12 months ago
Automatic Processor Lower Bound Formulas for Array Computations
In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequenc...
Peter R. Cappello, Ömer Egecioglu
ICS
1994
Tsinghua U.
15 years 11 months ago
Evaluating automatic parallelization for efficient execution on shared-memory multiprocessors
We present a parallel code generation algorithm for complete applications and a new experimental methodology that tests the efficacy of our approach. The algorithm optimizes for d...
Kathryn S. McKinley
IPPS
1999
IEEE
15 years 11 months ago
tmPVM - Task Migratable PVM
In this paper we introduce an implementation of PVM that exploits the homogeneity of a MPP network with userlevel task migration. The target machine is the Fujitsu AP3000. It is b...
C. P. Tan, Weng-Fai Wong, Chung-Kwong Yuen
GPC
2009
Springer
15 years 4 months ago
I/O Device Virtualization in the Multi-core era, a QoS Perspective
In this paper, we propose an extension to the I/O device architecture, as recommended in the PCI-SIG IOV specification, for virtualizing network I/O devices. The aim is to enable ...
J. Lakshmi, S. K. Nandy
IPPS
1999
IEEE
15 years 11 months ago
Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...
Alberto Ferreira de Souza, Peter Rounce