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84
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ICPP
2003
IEEE
15 years 3 months ago
Enabling Partial Cache Line Prefetching Through Data Compression
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
Youtao Zhang, Rajiv Gupta
ICPPW
2003
IEEE
15 years 3 months ago
Secure Bootstrapping and Routing in an IPv6-Based Ad Hoc Network
The mobile ad hoc network (MANET), which is characterized by an infrastructureless architecture and multi-hop communication, has attracted a lot of attention recently. In the evol...
Yu-Chee Tseng, Jehn-Ruey Jiang, Jih-Hsin Lee
105
Voted
IPPS
2003
IEEE
15 years 3 months ago
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
IPPS
2003
IEEE
15 years 3 months ago
Implementation of a Calendar Application Based on SyD Coordination Links
System on Devices (SyD) is a specification for a middleware to enable heterogeneous collections of information, databases, or devices (such as hand-held devices) to collaborate wi...
Sushil K. Prasad, Anu G. Bourgeois, Erdogan Dogdu,...
76
Voted
PODC
2003
ACM
15 years 3 months ago
Software transactional memory for dynamic-sized data structures
We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocki...
Maurice Herlihy, Victor Luchangco, Mark Moir, Will...