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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 6 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
TC
2008
14 years 9 months ago
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
Xiaogang Qiu, Michel Dubois
SIGMETRICS
2012
ACM
290views Hardware» more  SIGMETRICS 2012»
13 years 3 days ago
Power and energy containers for multicore servers
Energy efficiency and power capping remain growing concerns in server systems. Online applications continue to evolve with new features and dynamic clientdirected processing, res...
Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas, X...
ICDCSW
2003
IEEE
15 years 3 months ago
Dynamic Resource Control for High-Speed Downlink Packet Access Wireless Channel
It is a challenging task to provide Quality of Service (QoS) control for a shared high-speed downlink packet access (HSDPA) wireless channel. In this paper, we first propose a ne...
Huai-Rong Shao, Chia Shen, Daqing Gu, Jinyun Zhang...
68
Voted
ICS
2003
Tsinghua U.
15 years 2 months ago
miNI: reducing network interface memory requirements with dynamic handle lookup
Recent work in low-latency, high-bandwidth communication systems has resulted in building user–level Network InControllers (NICs) and communication abstractions that support dir...
Reza Azimi, Angelos Bilas