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ICS
2007
Tsinghua U.
15 years 3 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
68
Voted
ICS
2003
Tsinghua U.
15 years 2 months ago
Reducing register ports using delayed write-back queues and operand pre-fetch
In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these pararmeters g...
Nam Sung Kim, Trevor N. Mudge
87
Voted
PODC
2009
ACM
15 years 6 months ago
The wireless synchronization problem
In this paper, we study the wireless synchronization problem which requires devices activated at different times on a congested single-hop radio network to synchronize their roun...
Shlomi Dolev, Seth Gilbert, Rachid Guerraoui, Fabi...
80
Voted
IEEEPACT
2009
IEEE
15 years 4 months ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...
IEEEPACT
2008
IEEE
15 years 4 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...