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CDES
2006
184views Hardware» more  CDES 2006»
15 years 3 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
15 years 2 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
FGCS
2006
119views more  FGCS 2006»
15 years 2 months ago
OpenMP versus MPI for PDE solvers based on regular sparse numerical operators
Tw o parallel programming models represented b y OpenMP and MPI are compared for PDE solvers based on regular sparse numerical operators. As a typical representative of such an app...
Markus Nordén, Sverker Holmgren, Michael Th...
ISCA
2008
IEEE
143views Hardware» more  ISCA 2008»
15 years 2 months ago
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
Current hardware transactional memory systems seek to simplify parallel programming, but assume that large transactions are rare, so it is acceptable to penalize their performance...
Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael...
JPDC
2008
167views more  JPDC 2008»
15 years 2 months ago
A performance study of general-purpose applications on graphics processors using CUDA
Graphics processors (GPUs) provide a vast number of simple, data-parallel, deeply multithreaded cores and high memory bandwidths. GPU architectures are becoming increasingly progr...
Shuai Che, Michael Boyer, Jiayuan Meng, David Tarj...
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