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126
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EUROPAR
2001
Springer
15 years 6 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
109
Voted
HYBRID
2001
Springer
15 years 6 months ago
Assume-Guarantee Reasoning for Hierarchical Hybrid Systems
Abstract. The assume-guarantee paradigm is a powerful divide-andconquer mechanism for decomposing a veri cation task about a system into subtasks about the individual components of...
Thomas A. Henzinger, Marius Minea, Vinayak S. Prab...
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
15 years 6 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
97
Voted
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 6 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
110
Voted
MICRO
1999
IEEE
108views Hardware» more  MICRO 1999»
15 years 6 months ago
Exploiting ILP in Page-based Intelligent Memory
This study compares the speed, area, and power of di erent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processo...
Mark Oskin, Justin Hensley, Diana Keen, Frederic T...
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