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CJ
2006
84views more  CJ 2006»
15 years 4 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
JOCN
2011
80views more  JOCN 2011»
14 years 11 months ago
Neural Changes Associated with Nonspeech Auditory Category Learning Parallel Those of Speech Category Acquisition
■ Native language experience plays a critical role in shaping speech categorization, but the exact mechanisms by which it does so are not well understood. Investigating category...
Ran Liu, Lori L. Holt
PPAM
2005
Springer
15 years 9 months ago
Scheduling Moldable Tasks for Dynamic SMP Clusters in SoC Technology
Abstract. The paper presents an algorithm for scheduling parallel programs for execution in a parallel architecture based on dynamic SMP processor clusters with data transfers on t...
Lukasz Masko, Pierre-François Dutot, Gregor...
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SBACPAD
2003
IEEE
102views Hardware» more  SBACPAD 2003»
15 years 9 months ago
Performance Analysis of DECK Collective Communication Service
Collective communication is very useful for parallel applications, especially those in which matrix and vector data structures need to be manipulated by a group of processes. This...
Rafael Ennes Silva, Delcino Picinin, Marcos E. Bar...
TOG
2008
106views more  TOG 2008»
15 years 4 months ago
BSGP: bulk-synchronous GPU programming
We present BSGP, a new programming language for general purpose computation on the GPU. A BSGP program looks much the same as a sequential C program. Programmers only need to supp...
Qiming Hou, Kun Zhou, Baining Guo