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ICS
1999
Tsinghua U.
15 years 11 months ago
Reorganizing global schedules for register allocation
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
Gang Chen, Michael D. Smith
ICS
1999
Tsinghua U.
15 years 11 months ago
Low-level router design and its impact on supercomputer system performance
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
Valentin Puente, José A. Gregorio, Cruz Izu...
PAMI
2010
140views more  PAMI 2010»
15 years 5 months ago
Differential Geometric Inference in Surface Stereo
—Many traditional two-view stereo algorithms explicitly or implicitly use the frontal parallel plane assumption when exploiting contextual information since, e.g., the smoothness...
Gang Li, Steven W. Zucker
SPAA
2009
ACM
16 years 7 months ago
Brief announcement: selfishness in transactional memory
In order to be efficient with selfish programmers, a multicore transactional memory (TM) system must be designed such that it is compatible with good programming incentives (GPI),...
Raphael Eidenbenz, Roger Wattenhofer
ICSE
2003
IEEE-ACM
16 years 7 months ago
Computer-Assisted Assume/Guarantee Reasoning with VeriSoft
We show how the state space exploration tool VeriSoft can be used to analyze parallel C/C++ programs compositionally. VeriSoft is used to check assume/guarantee specifications of ...
Jürgen Dingel