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IPPS
2006
IEEE
15 years 10 months ago
Improving cache locality for thread-level speculation
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
Stanley L. C. Fung, J. Gregory Steffan
IPPS
2006
IEEE
15 years 10 months ago
A study of MPI performance analysis tools on Blue Gene/L
Applications on todays massively parallel supercomputers rely on performance analysis tools to guide them toward scalable performance on thousands of processors. However, conventi...
I-Hsin Chung, Robert Walkup, Hui-Fang Wen, Hao Yu
ASAP
2005
IEEE
96views Hardware» more  ASAP 2005»
15 years 10 months ago
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
A. Murat Fiskiran, Ruby B. Lee
ASPLOS
2004
ACM
15 years 10 months ago
Programming with transactional coherence and consistency (TCC)
Transactional Coherence and Consistency (TCC) offers a way to simplify parallel programming by executing all code within transactions. In TCC systems, transactions serve as the fu...
Lance Hammond, Brian D. Carlstrom, Vicky Wong, Ben...
HPDC
2002
IEEE
15 years 9 months ago
Distributed Computing with Load-Managed Active Storage
One approach to high-performance processing of massive data sets is to incorporate computation into storage systems. Previous work has shown that this active storage model is effe...
Rajiv Wickremesinghe, Jeffrey S. Chase, Jeffrey Sc...