5640 search results - page 605 / 1128 » Parallelizing the Data Cube |
178
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ISCAPDCS
2004
15 years 5 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
156
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HPCA
2008
IEEE
16 years 4 months ago
2008
IEEE
Multiprocessor computer systems are currently widely used in commercial settings to run critical applications. These applications often operate on sensitive data such as customer ...
125
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DASFAA
2008
IEEE
15 years 10 months ago
2008
IEEE
The DWS (Data Warehouse Striping) technique is a round-robin data partitioning approach especially designed for distributed data warehousing environments. In DWS the fact tables ar...
134
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
124
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IJCNN
2006
IEEE
15 years 10 months ago
2006
IEEE
— Over time, neural networks have proven to be extremely powerful tools for data exploration with the capability to discover previously unknown dependencies and relationships in ...