5640 search results - page 843 / 1128 » Parallelizing the Data Cube |
99
Voted
MICRO
1997
IEEE
15 years 5 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
111
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ISCA
1994
IEEE
15 years 4 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
107
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ICANNGA
2007
Springer
15 years 4 months ago
2007
Springer
Predictions computed by a classification tree are usually constant on axis-parallel hyperrectangles corresponding to the leaves and have strict jumps on their boundaries. The densi...
97
Voted
ARC
2006
Springer
15 years 4 months ago
2006
Springer
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
GECCO
2006
Springer
15 years 4 months ago
2006
Springer
A boosting algorithm based on cellular genetic programming to build an ensemble of predictors is proposed. The method evolves a population of trees for a fixed number of rounds an...