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» Parallelizing while loops for multiprocessor systems
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ICPPW
2009
IEEE
15 years 4 months ago
Multiprocessor Synchronization and Hierarchical Scheduling
Multi-core architectures have received significant interest as thermal and power consumption problems limit further increase of speed in single-cores. In the multi-core research ...
Farhang Nemati, Moris Behnam, Thomas Nolte
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
15 years 3 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
HPCA
2005
IEEE
15 years 10 months ago
Scatter-Add in Data Parallel Architectures
Many important applications exhibit large amounts of data parallelism, and modern computer systems are designed to take advantage of it. While much of the computation in the multi...
Jung Ho Ahn, Mattan Erez, William J. Dally
MICRO
1999
IEEE
143views Hardware» more  MICRO 1999»
15 years 2 months ago
Code Transformations to Improve Memory Parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
Vijay S. Pai, Sarita V. Adve
IEEEPACT
2008
IEEE
15 years 4 months ago
Multitasking workload scheduling on flexible-core chip multiprocessors
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
Divya Gulati, Changkyu Kim, Simha Sethumadhavan, S...