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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 7 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
TRIER
2002
14 years 9 months ago
Precise Interprocedural Dependence Analysis of Parallel Programs
It is known that interprocedural detection of copy constants and elimination of faint code in parallel programs are undecidable problems, if base statements are assumed to execute...
Markus Müller-Olm
FPL
2009
Springer
117views Hardware» more  FPL 2009»
15 years 2 months ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
IPPS
2006
IEEE
15 years 4 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
IPPS
1998
IEEE
15 years 2 months ago
Rendering Computer Animations on a Network of Workstations
Rendering high-quality computer animations requires intensive computation, and therefore a large amount of time. One way to speed up this process is to devise rendering algorithms...
Timothy D. Davis, Edward W. Davis