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SAMOS
2004
Springer
15 years 3 months ago
with Wide Functional Units
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
Miquel Pericàs, Eduard Ayguadé, Javi...
IPPS
1998
IEEE
15 years 2 months ago
Code Transformations for Low Power Caching in Embedded Multimedia Processors
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
Chidamber Kulkarni, Francky Catthoor, Hugo De Man
VISUALIZATION
1991
IEEE
15 years 1 months ago
Achieving Direct Volume Visualization with Interactive Semantic Region Selection
Interactive direct visualization of 3D data requires fast update rates and the ability to extract regions of interest from the surrounding data. We have implemented MultiValued Cl...
Terry S. Yoo, Ulrich Neumann, Henry Fuchs, Stephen...
HPCA
2003
IEEE
15 years 10 months ago
Variability in Architectural Simulations of Multi-Threaded Workloads
Multi-threaded commercial workloads implement many important internet services. Consequently, these workloads are increasingly used to evaluate the performance of uniprocessor and...
Alaa R. Alameldeen, David A. Wood
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 1 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun