Sciweavers

151 search results - page 29 / 31
» Parallelizing while loops for multiprocessor systems
Sort
View
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
15 years 4 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 2 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
HPCA
2009
IEEE
15 years 10 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
IPPS
2005
IEEE
15 years 3 months ago
Predicting Cache Space Contention in Utility Computing Servers
The need to provide performance guarantee in high performance servers has long been neglected. Providing performance guarantee in current and future servers is difficult because ï...
Yan Solihin, Fei Guo, Seongbeom Kim
ISCAS
2003
IEEE
167views Hardware» more  ISCAS 2003»
15 years 3 months ago
The multi-level paradigm for distributed fault detection in networks with unreliable processors
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
Krishnaiyan Thulasiraman, Ming-Shan Su, V. Goel