204 search results - page 11 / 41 » Parameterizations of Test Cover with Bounded Test Sizes |
FMICS
2006
Springer
15 years 2 months ago
2006
Springer
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
IASTEDSE
2004
15 years 3 days ago
2004
Pairwise coverage of factors affecting software has been proposed to screen for potential errors. Techniques to generate test suites for pairwise coverage are evaluated according ...
ICST
2009
IEEE
15 years 5 months ago
2009
IEEE
Constraint solving lies at the heart of several specification-based approaches to automated testing. Korat is a previously developed algorithm for solving constraints in Java pro...
ICCAD
1998
IEEE
15 years 3 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
ISSAC
2001
Springer
15 years 3 months ago
2001
Springer
The following questions are often encountered in system and control theory. Given an algebraic model of a physical process, which variables can be, in theory, deduced from the inp...